Cohesive Zone Model-Based Design Guidelines Against White Bump Failures

Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S. K., “Cohesive Zone Model-Based Design Guidelines Against White Bump Failures,” TECHCON, Austin, TX, Sep. 2014
The drive towards improved electrical performance led to the introduction of nano-porous ultra-low-k (ULK) dielectrics in back-end-of-line stack, present in microelectronic devices. However, these ULK layers have poor mechanical and adhesive strength. When a silicon chip is assembled on top of an organic substrate and cooled down from reflow temperature to room temperature, the stresses can be high enough to cause cracking of these interlayer dielectric layers in the vicinity of solder bump. Thus, cracking of ULK layers have become a primary reliability concern during flip-chip assembly reflow process. We present a cohesive zone element based finite-element model to predict initiation and propagation of the cracks observed in ULK layers as the flip-chip assembly is cooled down to room temperature. Furthermore, predictive models also look at the effect of die thickness and substrate properties to develop design guidelines aimed at reducing the risk of white-bump failures in future packages.
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