"Flip-chip on glass (FCOG) package for low warpage

McCann, S.R.; Sundaram, V.; Tummala, R.R.; Sitaraman, S.K., "Flip-chip on glass (FCOG) package for low warpage," Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th , vol., no., pp.2189,2193, 27-30 May 2014
As microelectronic industry moves toward stacking of dies to achieve greater performance in smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then to assemble the silicon interposers onto organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. The ongoing work at the Packaging Research Center is exploring the use of glass substrates as a superior alternative to organics in I/Os and to silicon in electrical performance. In addition, glass provides intermediate and tunable coefficient of thermal expansion between silicon and organic, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential substrate material. In this paper, we examine large glass panels as substrates for microelectronic packages through experiments and simulation. Starting with a 150 × 150 mm glass panel with a thickness in the range of 100 to 300 um μm, we have built alternating layers of dielectric and copper on both sides of the panel. The panels go through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 × 25 mm, and a 10 mm × 10 mm Si die with a peripheral staggered bump pitch of 80/40 um μm is then assembled on the glass substrate by thermocompression bonding with a pre-applied no-flow underfill. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical mod- ls have been developed. These models account for temperature-dependent properties of the dielectric as well as viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip-chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D and 2.5D systems.
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