Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu ICs
Submitted by Caspar_admin on Fri, 01/03/2014 - 20:32Citation:
Kacker K., Lo, G., and Sitaraman, S. K., “Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu ICs,” IMECE2006-ASME, November 2006, Chicago, IL, USA, IMECE2006-16014.