A Review of Two-Phase Forced Cooling in Three-Dimensional Stacked Electronics: Technology IntegrationSubmitted by Caspar_admin on Tue, 10/03/2017 - 13:42
Green, C., Kottke, P., Han, X., Woodrum, C., Sarvey, T., Asrar, P., Zhang, X., Joshi, Y., Fedorov, A., Sitaraman, S., and Bakir, M., “A Review of Two-Phase Forced Cooling in Three-Dimensional Stacked Electronics: Technology Integration,” Transactions of the ASME – Journal of Electronic Packaging, December 2015, Vol. 137, pp. 0408021- 0408029.
Three-dimensional (3D) stacked electronics present significant advantages from an electrical design perspective, ranging from shorter interconnect lengths to enabling heterogeneous integration. However, multitier stacking exacerbates an already difficult thermal problem. Localized hotspots within individual tiers can provide an additional challenge when the high heat flux region is buried within the stack. Numerous investigations have been launched in the previous decade seeking to develop cooling solutions that can be integrated within the 3D stack, allowing the cooling to scale with the number of tiers in the system. Two-phase cooling is of particular interest, because the associated reduced flow rates may allow reduction in pumping power, and the saturated temperature condition of the coolant may offer enhanced device temperature uniformity. This paper presents a review of the advances in two-phase forced cooling in the past decade, with a focus on the challenges of integrating the technology in high heat flux 3D systems. A holistic approach is applied, considering not only the thermal performance of standalone cooling strategies but also coolant selection, fluidic routing, packaging, and system reliability. Finally, a cohesive approach to thermal design of an evaporative cooling based heat sink developed by the authors is presented, taking into account all of the integration considerations discussed previously. The thermal design seeks to achieve the dissipation of very large (in excess of 500 W/cm2) background heat fluxes over a large 1 cm × 1 cm chip area, as well as extreme (in excess of 2 kW/cm2) hotspot heat fluxes over small 200 μm × 200 μm areas, employing a hybrid design strategy that combines a micropin–fin heat sink for background cooling as well as localized, ultrathin microgaps for hotspot cooling.