Reliability study of micro-pin fin array for on-chip cooling

Citation: 
Woodrum, D.C.; Sarvey, T.; Bakir, M.S.; Sitaraman, S.K., "Reliability study of micro-pin fin array for on-chip cooling," Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th , vol., no., pp.2283,2287, 26-29 May 2015
Abstract: 
With continued power, performance, functionality, and miniaturization demands, microelectronic devices can dissipate upwards of 50 W/cm2 reaching to 100's of W/cm2 and possibly 1000 W/cm2 in the next 10 years. With such a high heat flux, traditional cooling through thermal interface material and heat spreader may not be able to remove the heat, especially from hot spots. In an ongoing research at Georgia Tech, innovative fluid-thermal solutions are being pursued where deionized water or refrigerants are circulated through an array of micro-pin fins etched into the backside of the silicon. In the proposed configuration, the thick backside of the silicon is used to etch an array of micro-pin fins and the silicon die is then bonded to another silicon or quartz substrate to create a micro-pin fin channel for fluid flow. To maximize heat flux, the fluid is expected to be in two-phase. The objective of this paper is to examine such a micro-pin fin array from the standpoint of cracking and reliability.
Link to Paper: 
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7159922&sortType=desc_p_Publication_Year&matchBoolean=true&searchWithin%5B%5D=%22First+Name%22%3ASuresh&searchWithin%5B%5D=%22Middle+Name%22%3AK&searchWithin%5B%5D=%22Last+Name%22%3ASitaraman