"Study of cracking of thin glass interposers intended for microelectronic packaging substrates

Citation: 
McCann, S.R.; Sato, Y.; Sundaram, V.; Tummala, R.R.; Sitaraman, S.K., "Study of cracking of thin glass interposers intended for microelectronic packaging substrates," Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th , vol., no., pp.1938,1944, 26-29 May 2015
Abstract: 
Glass interposers have gained increased attention and interest in microelectronics industry since 2010. This is because glass has a tailorable coefficient of thermal expansion (CTE), high mechanical rigidity, availability in large and thin panel form, low processing cost, smooth surface for fine line and space fabrication, and superior electrical properties. While thin glass panels offer such a plethora of benefits, there are several processing and reliability challenges that glass imposes. As a brittle material, glass has low fracture toughness and is prone to cracking. In a typical large-area glass panel processing, layers of dielectric polymers and conducting copper are sequentially deposited and patterned. Due to these temperature histories and difference in the CTE among different materials, the panel is subjected to process-induced residual stresses. When the panel is subsequently diced into smaller substrates, the glass could crack. This cracking is due to high residual stresses as well as dicing defects and possible delamination at the polymer-glass interface. This experimental and theoretical work aims to investigate thin glass cracking and understand the mechanics of such cracks, focusing on the stresses induced by build-up layers. As part of this work, glass panels of 150 x 150 mm size and 100 μm thickness were laminated on both sides with ZS-100 polymer of 10 - 22.5 μm thickness and cured. After the lamination process, 5 - 10 μm thickness of copper is then deposited through a semi-additive electroless and electrolytic plating processes. This process of polymer and copper are repeated to create a total of two metal layers on each side of the panel. The panel is then diced into 18.4 x 18.4 mm substrate coupons. Dicing defects are characterized using optical inspection. Cracking failures are documented. The unbroken substrates are thermal cycled between -40 and 125 °C. In parallel to the experimental investigation, numerical- models are created based on the sequential fabrication process. Copper material properties are obtained from literature as well as from in-house nanoindentation tests. Polymer properties are obtained from vendor data, and the stress-free temperature is obtained through experiments. Dicing process is simulated by inserting a vertical crack through the panel, and various dicing defects are introduced in the singulated substrate. Energy available for crack propagation of such defects is determined through fracture mechanics approach, and design guidelines to mitigate glass fracture during dicing and reliability testing are explored.