Experimental and simulation study of double-sided flip-chip assembly with a stiffener ring

Citation: 
Liu, X., Li, M., Mulle, D.R., Cline, J., and Sitaraman, S.K.,"Experimental and simulation study of double-sided flip-chip assembly with a stiffener ring," IEEE Transactions on Devices and Materials Reliability, Vol 14, No 1, March 2014 p 512-522
Abstract: 
The microelectronic packaging field is moving into the third dimension for miniaturization, low power consumption, and better performance. In this paper, we present a double-sided flip-chip (FC) organic substrate with a memory controller on one side of the package and 3-D stacked disaggregated memory chips on the other side of the package. This design allows the controller to interface with the DRAM stack directly through the substrate providing the shortest possible interconnect path and thus achieving the fastest signaling speed. However, this double-sided FC configuration also causes yield, assembly, test, and reliability challenges. In order to optimize the assembly process, elastic and viscoelastic sequential 3-D finite-element models are developed to simulate the package assembly process and are validated experimentally. In these simulations, various assembly process sequences are simulated with different conditions.
Link to Paper: 
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6606807&queryText%3DExperimental+and+simulation+study+of+double-sided+flip-chip+assembly+with+a+stiffener+ring