Double-side process and reliability of through-silicon vias for passive interposer applications

Citation: 
Chen, Q., Liu, X., Sundaram, V., Sitaraman, S. K., and Tummala, R. R.,"Double-side process and reliability of through-silicon vias for passive interposer applications," IEEE Transactions on Device and Materials Reliability, Vol 14, No. 4, December 1, 2014. p 1041-1048,
Abstract: 
Through-silicon vias (TSVs) for passive interposer applications are being widely developed in industry and academia. This paper for the first time presents a double-side process to fabricate such TSVs. Such a process has many benefits, including not requiring carrier wafers for a wafer size between 150 and 200 mm and avoiding the chemical mechanical polishing processes after Cu plating. It thus significantly reduces the fabrication process steps compared with a traditional TSV. The reliability of TSVs formed this way has been studied by fabricating daisy chains and testing them for temperature cycling. Detailed mechanical failure mechanism analysis by a scanning electron microscope has been also carried out. In addition, finite-element models have been developed to analyze the fabrication-induced stresses and to estimate the thermomechanical reliability of the fabricated TSV structures
Link to Paper: 
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6915697