Response Surface and Multiobjective Optimization Methodology for the Design of Compliant InterconnectsSubmitted by Caspar_admin on Tue, 11/11/2014 - 16:24
Chen, W. and Sitaraman, S. K., “Response Surface and Multi-objective Optimization Methodology for the Design of Compliant Interconnects”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 4, No. 11, November 2014, pp.1769-1777
Compliant off-chip interconnects have both in-plane and out-of-plane compliance and are able to accommodate the differential deflection between the die and the substrate or between the substrate and the board, and thus can enhance overall reliability and life of a microelectronic system. A TriDelta compliant interconnect is being pursued at Georgia Tech as an alternate die-to-substrate or substrate-to-board interconnect. It is found that any geometry improvement that enhances the mechanical compliance will also adversely affect the electrical performance. Thus, the design of a compliant interconnect is a tradeoff between the mechanical and electrical performances. In this paper, we examine eight design variables to balance mechanical and electrical performance metrics of a TriDelta interconnect. These design variables are appropriately reduced to four and normalized. The method of normalization not only reduces the number of the design variables but also makes the response surfaces scalable with footprint size. The response surfaces are constructed for electrical resistance, inductance, and the von Mises strains using the central composite inscribed design points. The method of global criterion is used to scalarize this multiobjective optimization problem, and an optimization has been done using specified design and processing constraints as well as the ranges of the design variables. Based on the optimization results, it is seen that the TriDelta compliant interconnect geometry can be designed to meet all of the electrical, mechanical, and fabrication requirements. The developed methodology is applicable to a wide range of other compliant interconnects beyond what is presented in this paper.