Electrical Design of Wafer Level Package on Board for Gigabit Data Transmission

Citation: 
Kim, W, Madhavan, R., Mao, J., Choi, J., Choi, S., Ravi, D., Sundaram, V., Sankararaman, S., Gupta, P., Zhang, Z., Lo, G., Swaminathan, M., Tummala, R. R., Sitaraman, S., Wong, C. P., Iyer, M. K., Rotaru, M., and Tay, A. A. O., “Electrical Design of Wafer Level Package on Board for Gigabit Data Transmission,” Proceedings of EPTC 2003, 5th Electronics Packaging Technology Conference, IEEE-CPMT and IMAPS, Dec. 10-12, 2003, Singapore, pp. 150-159.