G-Helix: Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects

Citation: 
Lo, G. and Sitaraman, S. K., "G-Helix: Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 320-325