Chip-Package Co-Design: Effect of Substrate Warpage on BEOL Reliability

Citation: 
Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S., “Chip-Package Co-Design: Effect of Substrate Warpage on BEOL Reliability,”Proceedings of the ASME 2013 International Mechanical Engineering Congress and Exposition (IMECE2013), November 2013, San Diego, CA, IMECE2013-65877.