Silicon and Nano-Scale Metal Interface Characterization using Stress-Engineered Superlayer Test Methods

Citation: 
Zheng, J., Modi, M., Ginga, N., and Sitaraman, S. K., “Silicon and Nano-Scale Metal Interface Characterization using Stress-Engineered Superlayer Test Methods,” IEEE Transactions on Components and Packaging Technologies, Vol. 32, No. 2, June 2009, pp. 333-338. Also, Zheng, J., Modi, M., Ginga, N., and Sitaraman, S., “Silicon, Low-K Dielectric, and Nano-Scale Metal Interface Characterization using Stress-Engineered Superlayer Test Methods,” 57th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Reno, NV, May 2007, pp. 1384-1389.