Failure Analysis of Through-Silicon Vias in Free-standing Wafer under Thermal-Shock Test

Citation: 
Liu, X, Chen, Q., Sundaram, V., Tummala, R. R., and Sitaraman, S. K., “Failure Analysis of Through-Silicon Vias in Free-standing Wafer under Thermal-Shock Test,” Microelectronics Reliability, http://dx.doi.org/10.1016/j.microrel.2012.06.140, 2012 (online); Volume 53, Issue 1, January 2013, pp. 70–78.