Journal Publications

Journal Publications

  1. Chen, Q., Liu, X., Sundaram, V., Sitaraman, S. K., and Tummala, R. R.,"Double-side process and reliability of through-silicon vias for passive interposer applications," IEEE Transactions on Device and Materials Reliability, Vol 14, No. 4, December 1, 2014. p 1041-1048, view
  2. Chen, W. and Sitaraman, S. K., “Response Surface and Multi-objective Optimization Methodology for the Design of Compliant Interconnects”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 4, No. 11, November 2014, pp.1769-1777 view
  3. Liu, X. Thadesar, P.A., Taylor, C.L., Oh, H.Kunz, M., Tamura, N., Bakir, M.S., and Sitaraman, S.K. "In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffracton exploring the physics behind data interpretation." Applied Phyiscs Letter, September 2014, Vol. 105, Iss. 11, 112109 view
  4. Tian, Y., Liu, X., Chow, J., Wu, Y.P, and Sitaraman, S.K.."Experimental evaluation of SnAgCu solder joint reliability in 100 micron pitch flip chip assemblies." Microelectronics Reliability, May 2014, Vol. 54, p 939-944. view
  5. Raghavan, S., Schmadlak, I., Leal, G. and Sitaraman, S.K. Study of chip-package interaction parameters on interlayer dielectric crack propagation." IEEE Transactions on Device and Materials Reliability, March 2014, Vol. 14, pp. 57-65. view
  6. Liu, X., Li, M., Mulle, D.R., Cline, J., and Sitaraman, S.K.,"Experimental and simulation study of double-sided flip-chip assembly with a stiffener ring," IEEE Transactions on Devices and Materials Reliability, Vol 14, No 1, March 2014 p 512-522 view
  7. Ginga, N., Chen, W., and Sitaraman, S. K. , “Waviness Reduces Effective Modulus of Carbon Nanotube Forests by Several Orders of Magnitude”, In: Carbon, vol.66, pp.57-66, January 2014 view
  8. Okereke, R., Kacker, K., and Sitaraman, S. K., “Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects,” ASME Journal of Electronic Packaging, Sep. 2013, Vol. 135, pp. 031004-1 to 031004-7. view
  9. Liu, X., Thadesar, P. A., Taylor, C. L., Kunz, M., Tamura, N., Bakir, M. S., and Sitaraman, S. K., "Dimension and Liner Dependent Thermomechanical Strain Characterization of Through-Silicon Vias using Synchrotron X-ray Diffraction," Journal of Applied Physics, Vol. 114, p. 064908, 2013. view
  10. Tian, Y., Liu, X., Chow, J. Wu, Y-P, and Sitaraman, S. K., “Comparison of Sn-Ag-Cu Solder Alloy Intermetallic Compound Growth under Different Thermal Excursions for Fine-Pitch Flip-Chip Assemblies,” Journal of Electronic Materials, Vol. 42, No. 8, August 2013, pp. 2724-2731. view
  11. Chen, W., Okereke, R., and Sitaraman, S. K., “Compliance Analysis of Multi-Path Fan-Shaped Interconnects,” Microelectronics Reliability Vol. 53, 2013, pp. 964–974. view
  12. Liu, X, Chen, Q., Sundaram, V., Simmons-Matthews, M., Wachtler, K. P., Tummala, R. R., and Sitaraman, S. K., “Reliability Assessment of Through Silicon Vias in Multi-Die Stack Packages,” IEEE Transactions on Device and Materials Reliability Vol. 12, No. 2, June 2012, pp. 263-271. view
  13. Liu, X., Thadesar, P. A., Taylor, C. L., Kunz, M., Tamura, N., Bakir, M. S., and Sitaraman, S. K., "Thermomechanical Strain Measurement by Synchrotron X-ray Diffraction and Data Interpretation for Through-Silicon Vias," Applied Physics Letters, Vol.103, p.022107, 2013. view
  14. Lin, Z., Liu, Y., Raghavan, S., Moon, K.-S., Sitaraman, S. K., and Wong, C. P., “Magnetic Alignment of Hexagonal Boron Nitride Platelets in Polymer Matrix: Toward High Performance Anisotropic Polymer Composites for Electronic Encapsulation,” American Chemical Society (ACS) Applied Materials and Interfaces, 2013, Vol. 5, pp. 7633-7640. view
  15. Ginga, N. J. and Sitaraman, S. K., “The experimental measurement of effective compressive modulus of carbon nanotube forests and the nature of deformation,” Carbon, ,Volume 53, March 2013, pp. 237–244 view
  16. Tian, Y., Chow, J., Liu, X., Wu, Y.P., and Sitaraman, S.K., "Study of intermetallic growth and kinetics in fine-pitch lead-free solder bumps for next-generation flip-chip assemblies," Journal of Electronic Materials, Vol. 42, pp. 230-239, February 2013. view
  17. Liu, X, Chen, Q., Sundaram, V., Tummala, R. R., and Sitaraman, S. K., “Failure Analysis of Through-Silicon Vias in Free-standing Wafer under Thermal-Shock Test,” Microelectronics Reliability, http://dx.doi.org/10.1016/j.microrel.2012.06.140, 2012 (online); Volume 53, Issue 1, January 2013, pp. 70–78. view
  18. Ostrowicki, G. T. and Sitaraman, S. K., “Magnetically actuated peel test for thin films,” Thin Solid Films, 520 (2012), pp. 3987–3993. view
  19. Ostrowicki, G. T., Fritz, N. T., Okereke, R. I., Kohl, P. A., and Sitaraman, S. K., “Domed and Released Thin Film Construct – An Approach for Material Characterization and Compliant Interconnects,” IEEE Transactions on Device and Materials Reliability,” Vol. 12, No. 1, March 2012, pp. 15-23. view
  20. Raghavan, S., Okereke, R. I., and Sitaraman, S., K., “An Efficient Implementation of Polymer Viscoelastic Behavior through a Pseudo Viscoelastic Model,” IMAPS Journal of Microelectronic Packaging, 2011, Vol. 8, No. 2, pp. 83-87. view
  21. Raghavan, S., Klein, K., Yoon, S., Kim, J.-D., Moon, K.-S., Wong, C. P., and Sitaraman, S. K., “Methodology to Predict Substrate Warpage and Different Techniques to Achieve Substrate Warpage Targets ,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 7, July 2011, pp. 1064-1074. view
  22. Ginga, N. and Sitaraman, S. K., “New Method to Measure Tensile Strength of Low Modulus Thin Films,” Letters in Fracture and Micromechanics, International Journal of Fracture, Vol. 170, Issue 2, 2011, pp. 199-206. view
  23. Zheng, J., Ostrowicki, G., and Sitaraman, S. K., “Cyclic Magnetic Actuation for Potential Characterization of Interfacial Fatigue Fracture,” IEEE Transactions on Components and Packaging Technologies, Vol. 33, No. 3, 2010, pp. 648-654. Also Zheng, J., Ostrowicki, G., and Sitaraman, S. K., “Non-contact magnetic actuation test technique to characterize interfacial fatigue fracture of thin films,” 59th Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2009, pp. 1368-1373. view
  24. Tunga, K. and Sitaraman, S. K., "Fatigue Life Prediction of Lead-free Solders using Laser Moiré Interferometry," Microelectronics Reliability, Vol. 50, Issue 12, Dec. 2010, pp. 2026-2036. view
  25. Liu, X., Zheng, J., and Sitaraman, S. K., “Hygro-Thermo-Mechanical Reliability Assessment of a Thermal Interface Material for a Ball Grid Array Package Assembly,” Transactions of the ASME – Journal of Electronic Packaging, June 2010, Vol. 132, pp. 0210041-0210048. view
  26. Tunga, K. and Sitaraman, S. K., "Predictive Model Development for Life Prediction of PBGA Packages with SnAgCu Solder Joints." IEEE Transactions on Components and Packaging Technologies, Vol. 33, No. 1, 2010, pp. 84-93. view
  27. Kim, I., Peak, R., and Sitaraman, S. K, “ROM: A Reliability Knowledge Representation For Collaborative System Design,” Engineering with Computers, Vol. 26, No. 1, 2010, pp. 11-23. view
  28. Kacker, K. and Sitaraman, S. K., "Reliability Assessment and Failure Analysis of G-Helix, A Free-Standing Compliant Off-Chip Interconnect," Journal of Microelectronics and Electronic Packaging, Vol. 6, No. 1, pp. 59-65, 2009. view
  29. McCaslin, L., Yoon, S., Kim, H., and Sitaraman, S. K., “Methodology for Modeling Substrate Warpage Using Copper Trace Pattern Implementation," IEEE Transactions on Advanced Packaging, Vol. 32, No. 4, Nov. 2009, pp. 740-745. Also, McCaslin, L. and Sitaraman, S. K., “Methodology for Modeling Substrate Warpage Using Copper Trace Pattern Implementation,” 58th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2008, pp. 1582-1586. view
  30. Klein, K., Ostrowicki, G., Gewirtz, A., and Sitaraman, S. K., “Fabrication and Bio-conjugation of Micro- and Nano-Scale Structures Intended for Cancer-Specific Antigen Detection,” Transactions of the ASME – Journal of Electronic Packaging, Vol. 131, June 2009, 0210141-0210146. Also, Klein, K., Ostrowicki, G., Gewirtz, A., and Sitaraman, S. K., “Micro and Nano Thin Film Devices as Bio-Assays for Cancer Diagnosis,” IMECE2006-ASME, November 2006, Chicago, IL, USA, IMECE2006-15581. view
  31. Zheng, J., Modi, M., Ginga, N., and Sitaraman, S. K., “Silicon and Nano-Scale Metal Interface Characterization using Stress-Engineered Superlayer Test Methods,” IEEE Transactions on Components and Packaging Technologies, Vol. 32, No. 2, June 2009, pp. 333-338. Also, Zheng, J., Modi, M., Ginga, N., and Sitaraman, S., “Silicon, Low-K Dielectric, and Nano-Scale Metal Interface Characterization using Stress-Engineered Superlayer Test Methods,” 57th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Reno, NV, May 2007, pp. 1384-1389. view
  32. Kacker, K. and Sitaraman, S. K., "Electrical/Mechanical Modeling, Reliability Assessment and Fabrication of FlexConnects: A MEMS based Compliant Chip-to-Substrate Interconnect," IEEE/ASME Journal of Microelectromechanical Systems, Vol. 18, No. 2, April 2009, pp. 322-331. view
  33. Modi, M., Ginga, N., and Sitaraman, S. K., “Micro-Contact Spring Reliability: Design Against Interfacial Fracture." IEEE Transactions on Components and Packaging Technologies, Vol. 32, No. 1, March 2009, pp. 197-206. view
  34. Zheng, J. and Sitaraman, S. K., “Use of Stress-Engineered Material Layers for the Measurement of Interfacial Fracture Toughness of Nano-Scale Thin Films,” International Journal on Materials and Product Technology, Special Issue on Micro/NanoElectronics and NEMS and MEMS Packaging, Vol. 34, No. 1/2, pp. 131-138, 2009. view
  35. Kacker, K. and Sitaraman, S.K., “Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects” IEEE Transactions on Component and Packaging Technologies, Vol. 31, No. 4, 2008, pp. 816-823. view
  36. Tunga, K. and Sitaraman, S. K., “Microstructure Evolution based Acceleration Factor Determination for SnAgCu Solder Joints during Thermal Cycling,” International Journal of Materials and Structural Integrity, Vol. 2, Issue 1, 2008, pp. 173-192. view
  37. Kim, I., Pucha, R. V., Peak, R., and Sitaraman, S. K., “Development of Reliability Allocation and Assessment Algorithms for Designing Multi-Level Microelectronic Systems,” Journal of Microelectronics and Electronic Packaging, Vol. 5(1), 2008, pp. 12-25. view
  38. Tunga, K. and Sitaraman, S. K., "Using Carrier Fringes to Study the High Temperature Deformation Behavior of a BGA Package under Extended Dwell Times," Experimental Mechanics, 48(3), 2008, pp. 355-365. view
  39. Hegde, S., and Sitaraman, S. K., “Thermal Aging Reliability of Package-Level Polymer Optical Waveguides,” IEEE Transactions on Advanced Packaging, Vol. 31, No. 2, 2008, pp. 410-416. view
  40. Zeng, S., Peak, R., Xiao, A., and Sitaraman, S. “ZAP:A Knowledge-Based FEA Modeling Method for Highly Coupled Variable Topology Multi-Body Problems,” Engineering with Computers, Springer, 2008, DOI: 10.1007/s00366-007-0086-6. view
  41. Mahalingam, S., Prabhakumar, A., Tonapi, S., and Sitaraman, S. K., "Theoretical Modeling and Prediction of Delamination in Flip-Chip Assemblies with Nano-filled, No-flow Underfill Materials", Transactions of ASME - Journal of Electronic Packaging, Vol. 130, Vol. 4, Dec. 2008, pp. 0410051-0410055. view
  42. Perkins, A. and Sitaraman, S.K. "Analysis and Prediction of Vibration-Induced Solder Joint Failure for a Ceramic Column Grid Array (CCGA) Package," Transactions of ASME - Journal of Electronic Packaging, Vol. 130, No. 1, 2008, pp. 011012-1-11. view
  43. Kacker, K., Lo, G., Sitaraman, S.K., “Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects,” IEEE Transactions on Advanced Packaging, Vol. 31, No. 1, 2008, pp. 22-32. view
  44. Perkins, A. and Sitaraman, S. K., “Universal Fatigue Life Prediction Equation for Ceramic Ball Grid Array (CBGA) Packages,” Microelectronics Reliability, Vol./Issue 47/9-11, 2007, pp. 1353-1367. view
  45. Lee, K. J., Damani, M., Pucha, R., Bhattacharya, S., Tummala, R., and Sitaraman, S. K., "Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 1, 2007, pp. 152-162. view
  46. Kacker, K., Sokol, T., Yun, W., Swaminathan, M., and Sitaraman, S. K., “A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance," Transactions of the ASME – Journal of Electronic Packaging, Vol. 129, Dec. 2007, pp. 460-468. view
  47. Tunga, K. and Sitaraman, S. K., “An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls,” Transactions of the ASME – Journal of Electronic Packaging, Vol. 129, Dec. 2007, pp. 427-433. Also, Tunga, K. and Sitaraman, S. K., “Thermo-Mechanical Fatigue Life Estimation of Organic BGA Packages using Laser Moiré Interferometry,” IMECE2006-ASME, November 2006, Chicago, IL, USA, IMECE2006-13615. view
  48. Kumbhat, N.P., Raj, M.P., Pucha, R.V., Tsai, J.Y., Atmur, S., Bongio, E., Sitaraman, S.K., and Tummala, R.R., “Novel Ceramic Composite Substrates for High-Density and High Reliability Packaging,” IEEE Transactions on Advanced Packaging, Vol. 30, No. 4, Nov. 2007, pp. 641-653. view
  49. Hegde, S., Liu, F., Chang, G. K., and Sitaraman, S. K., “Optical Loss Changes in Siloxane Polymer Waveguides during Thermal Curing,” Journal of Applied Polymer Science, Volume 106, Issue 4, November 2007, pp. 2320-2327. view
  50. Hegde, S. and Sitaraman, S. K., “Stress-Induced Birefringence in Siloxane Polymer Waveguides,” Applied Physics Letters, Vol. 91, No. 8, Aug. 2007. view
  51. Zheng, J. and Sitaraman, S. K., “Fixtureless Superlayer-driven Delamination Test for Nanoscale Thin Film Interfaces,” Thin Solid Films, Volume 515, Issue 11, April 2007, pp. 4709-4716. view
  52. Perkins, A., Tunga, K., and Sitaraman, S. K., “Acceleration Factor to Relate Thermal Cycles to Power Cycles for Ceramic Ball Grid Area Array Packages,” IMAPS Journal of Microelectronics and Electronic Packaging, Vol. 3, No. 4, 2006, pp. 177-193. view
  53. Mahalingam, S., Goray, K., Tonapi, S., and Sitaraman, S. K., "Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials,” Transactions of ASME - Journal of Electronic Packaging, Vol. 128, Dec. 2006, pp. 405-411. view
  54. Varadharajan, M. G., Lee, K. J., Bhattacharya, S. K., Pucha, R., Tummala, R. R., and Sitaraman, S., ”Printed circuit board (PCB) miniaturization by embedded passives and sequential build-up (SBU) process methodology,” Journal of Indian Institute Science, Nov.-Dec. 2006, Vol. 86, pp. 639-654. view
  55. Pucha, R., Ramakrishna, G., Mahalingam, S., and Sitaraman, S. K., “Modeling Spatial Strain Gradient Effects in Thermo-mechanical Fatigue of Copper Microstructures,” International Journal of Fatigue, Vol. 26, 2004, pp. 947-957. view
  56. Modi, M and Sitaraman, S. K., “Single-Sample Decohesion Test: Mechanics and Implementation,” International Journal of Fracture, Vol. 129, 2004, pp. 1-20. view
  57. Modi, M and Sitaraman, S. K., "Interfacial fracture toughness measurement for thin film interfaces," Engineering Fracture Mechanics, Vol. 71, 2004, pp. 1219-1234. view
  58. Modi, M and Sitaraman, S. K., "Interfacial Fracture Toughness Measurement of a Ti/Si Interface," Transactions of ASME - Journal of Electronic Packaging, Vol. 126, Sep. 2004, pp. 301-307. view
  59. Pucha, R. V., Tunga, K., Pyland, J., and Sitaraman, S. K., “Accelerated Thermal Cycling Guidelines for Electronic Packages in Military Avionics Thermal Environment,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 126, June 2004, pp. 256-264. view
  60. Zhu, Q., Ma, L., and Sitaraman, S. K., “Development of G-helix structure as off-chip Interconenct,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 126, June 2004, pp. 237-246. view
  61. Hegde, S., Pucha, R. and Sitaraman, S. K., “Enhanced Reliability of High Density Wiring (HDW) Substrates through New Base Substrate and Dielectric Materials," Journal of Material Science: Materials in Electronics Vol. 15, Issue 5, May 2004, pp. 287-296. view
  62. Tummala, R. R., Swaminathan, M., Tentzeris, M., Laskar, J., Chang, G. K., Sitaraman, S. K., Keezer, D., Guidotti, D., Huang, Z., Lim, K., Wan, L., Bhattacharya, S., Sundaram, V., Liu, F., and Raj, P. M., "The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade," IEEE Transactions on Advanced Packaging, Vol. 27. No. 2, May 2004, pp 250-267. view
  63. Pucha, R. V., Hegde, S., Damani, M., Tunga, K., Perkins, A., Mahalingam, S., Lo, G., Klein, K., Ahmad, J., and Sitaraman, S. K., "System-Level Reliability Assessment of Mixed-Signal Convergent Microsystems," IEEE Transactions on Advanced Packaging, Vol. 27. No. 2, May 2004, pp 438-452. view
  64. Zhang, Z., Sitaraman, S. K., and Wong, C. P., “FEM Modeling of Temperature Distribution of a Flip-Chip No-Flow Underfill Package during Solder Reflow Process,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 27, No. 1, January 2004, pp. 86-92. view
  65. Shan, Z. and Sitaraman, S. K., “Elastic-Plastic Characterization of Thin Films using Nanoindentation Technique,” Thin Solid Films, 2003, Vol.437, pp. 176-181. view
  66. Xie, W. and Sitaraman, S. K., “Investigation of Interfacial Delamination of a Copper-Epoxy Interface under Monotonic and Cyclic Loading: Modeling and Evaluation,” IEEE Transactions on Advanced Packaging, Vol. 26, No. 4, Nov. 2003, pp. 441-446. view
  67. Zhu, Q., Ma, L., and Sitaraman, S. K., “Design and Fabrication of β-fly: a Chip-to-Substrate Interconnect,” IEEE Transactions on Components and Packaging Technologies, Vol. 26, No. 3, September 2003, pp. 582-590. view
  68. Ahmad, M. and Sitaraman, S. K., “Study of Coupled Thermal Electric Behavior of Compliant Micro-Spring Interconnects For Next Generation Probing Applications,” IEEE Transactions on Components and Packaging Technologies, Vol. 26, No. 2, June 2003, pp. 407-415. view
  69. Xie, W. and Sitaraman, S. K., “An Experimental Technique to Determine Critical Stress Intensity Factor,” Engineering Fracture Mechanics, Vol. 70, June 2003, pp. 1193-1201. view
  70. Zhu, Q., Ma, L., and Sitaraman, S. K., “Design Optimization of One-Turn Helix - a Novel Compliant Off-Chip Interconnect,” IEEE Transactions on Advanced Packaging, Vol. 26, No. 2, May 2003, pp. 106-112. view
  71. Dunne, R. C., Sitaraman, S. K., Luo, S., Wong, C. P., Estes, W. E., and Periyasamy, M., “Cure Kinetics Modeling and Process Optimization of the ViaLux 81 Epoxy Photo-Dielectric Dry Film (PDDF) Material for Microvia Applications,” Journal of Applied Polymer Science, Vol. 84, pp. 691-700, 2002. view
  72. Ahmad, M. and Sitaraman, S. K., “Study of Mechanical Behavior of Compliant Micro-Springs for Next-Generation Probing Applications,” Transactions of the ASME - Journal of Electronic Packaging Vol. 124, December 2002, pp. 411-418. view
  73. Ahmad, M. and Sitaraman, S. K., “Study of Mechanical Behavior of Compliant Micro-Springs for Next-Generation Probing Applications,” Transactions of the ASME - Journal of Electronic Packaging Vol. 124, December 2002, pp. 411-418. view
  74. Pyland, J., Pucha, R. V., and Sitaraman, S. K., “Thermo-Mechanical Reliability of Underfilled BGA Packages,” IEEE Transactions on Components and Packaging Technologies, Vol. 25, No. 2, April 2002, pp. 100-106. view
  75. Xie, W., Hu, H., and Sitaraman, S. K., “Role of Base Substrate Material on Dielectric and Copper Interlayer Separation,” The IMAPS International Journal of Microcircuits and Electronic Packaging, Vol. 25, No. 1, 2002, pp. 160-177. view
  76. Dunne, R. C., Sitaraman, S. K., Luo, S., Wong, C. P., Estes, W. E., Periyasamy, M., Coburn, J. C., “Thermal and Mechanical Characterization of ViaLux 81: A Novel Epoxy Photo-Dielectric Dry Film (PDDF) for Microvia Applications,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 592-600. IEEE Transactions – Components and Packaging Technologies, Vol. 24, No. 3, Sep. 2001, pp. 436-444. view
  77. Pucha, R. V., Pyland, J., and Sitaraman, S. K., “Damage Metric-Based Mapping Approaches for Developing Accelerated Thermal Cycling Guidelines for Electronic Packages,” International Journal of Damage Mechanics, July 2001, Vol. 10, pp. 214-234. view
  78. Harries, R. J. and Sitaraman, S. K., “Numerical Modeling of Interfacial Delamination Propagation in a Novel Peripheral Array Package,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 2, June 2001, pp. 256-264. view
  79. Sundararaman, V. and Sitaraman, S. K., “Interfacial Fracture Toughness for Delamination Growth Prediction in a Novel Peripheral Array Package,” IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 2, June 2001, pp. 265-270. view
  80. Dunne, R. C., Sitaraman, S. K., Luo, S., Rao, Y., Wong, C. P., Estes, W. E., Gonzalez, C. G., Coburn, J. C., and Periyasamy, M., “Investigation of the Curing Behavior of a Novel Epoxy Photo-Dielectric Dry Film (ViaLux 81) for High Density Interconnect Applications”, Journal of Applied Polymer Science, Vol. 78, 2000, pp. 430-437. view
  81. Sitaraman, S. K., Raghunathan, R., and Hanna, C. E., “Development of Virtual Reliability Methodology for Area-Array Devices used in Implantable and Automotive Applications,” IEEE Transactions on Components and Packaging Technologies, Vol. 23, No. 3, Sep. 2000, pp. 452-461. view
  82. Variyam, M., Xie, W., and Sitaraman, S. K., “Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 122, June 2000, pp. 121-127. view
  83. Dunne, R. C. and Sitaraman, S. K., “An Integrated Process Modeling Methodology and Module for Sequential Multilayered Substrate Fabrication using a Coupled Cure-Thermal-Stress Analysis Approach,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1311-1319. Also, IEEE Transactions – Electronics Packaging Manufacturing, Vol. 25, No. 4, 2002, pp. 326-334. view
  84. Xie, W. and Sitaraman, S. K., “Interfacial Thermal Stress Analysis of Anisotropic Multi-Layered Electronic Packaging Structures,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 122, March 2000, pp. 61-66. view
  85. Wu, J., Pike, R. T., Sitaraman, S., and Wong, C. P., “New Reworkable High-Temperature Low-Modulus Adhesives for MCM-D Assembly,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 122, March 2000, pp. 55-60. view
  86. Variyam, M. and Sitaraman, S. K., “Enhancing the Package Reliability through Design of Simulations Approach,” The IMAPS International Journal of Microcircuits and Electronic Packaging, No. 4, Vol. 22, 1999. view
  87. Sundararaman, V. and Sitaraman, S. K., “Determination of Fracture Toughness for Metal/Polymer Interfaces,” Transactions of the ASME - Journal of Electronic Packaging, Vol. 121, December 1999, pp. 275-281. view
  88. Michaelides, S. and Sitaraman, S. K., “Die Cracking and Reliable Die Design for Flip-Chip Assemblies,” IEEE Transactions on Advanced Packaging, IEEE-Components, Packaging, and Manufacturing Technology Society, Vol. 22, No. 4, November 1999, pp. 602-613. view
  89. Variyam, M., Sundararaman, V., Sitaraman, S. K., Wong, C. P., Wu, J., and Pike, R. T., “High-Temperature, Low-Modulus Adhesive Attach for Large-Area Thin-Film Processing on Silicon and Alumina Tiles,” IEEE Transactions on Electronics Packaging Manufacturing, IEEE-Components, Packaging, and Manufacturing Technology Society, Vol. 22, No. 4, Oct. 1999, pp. 290-294. view
  90. Schubert, A., Dudek, R., Leutenbauer, R., Doring, R., Kloeser, J., Oppermann, H., Michel, B., Reichl, H., Baldwin, D. F., Qu, J., Sitaraman, S., Swaminathan, M., Wong, C. P., and Tummala, R., "Do Chip Size Limits Exist for DCA?" IEEE Transactions on Electronics Packaging Manufacturing, IEEE-Components, Packaging, and Manufacturing Technology Society, Vol. 22, No. 4, Oct. 1999, pp. 255-263. view
  91. Johnson, C., Smith, K. and Sitaraman, S. K., “A Modeling Method for the Study of Thermo-Mechanical Behavior of HDI Vias,” The IMAPS International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 2, Second Quarter 1998, pp. 177-185. view
  92. Sitaraman, S. K. and Sizemore, J., ”Solder Shock Test Modeling,” The IMAPS International Journal of Microcircuits and Electronic Packaging, Vol. 20, No. 2, Second Quarter 1997, pp. 174-186. view
  93. Dunne, R. C. and Sitaraman, S. K., “Warpage and Interfacial Stress Distribution in a Single-Level Integrated Module (SLIM)”, Transactions of the ASME - Journal of Electronic Packaging, Vol. 119, Sep. 1997, pp.197-203. view
  94. Sitaraman, S. K., Kinzel, G. L., and Altan, T., "A Knowledge-Based System for Process Sequence Design in Axisymmetric Sheet Metal Forming," Journal of Materials Processing Technology, Vol. 25, pp. 247-271, 1991. view
  95. Tavoularis, S., Sitaraman, S., and Prinos, P., "Measurement of Turbulent Flow in Rod Bundle Subchannels," International Journal of Engineering Fluid Mechanics, 1988, pp.471-494. view