Conference Papers

Conference

  1. Abbaspour, R., Woodrum, D. C., Kottke, P. A., Sarvey, T. E., Green, C. E., Joshi, Y. K., Fedorov, A. G., Sitaraman, S. K., and Bakir, M. S., “Combined finned microgap with dedicated extreme-microgap hotspot flow for high performance thermal management,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV, pp. 1388-1392. view
  2. Song, Y., Abbaspour, R., Bakir, M., and Sitaraman, S. K., “Thermal Annealing Effects on Copper Microstructure in Through–Silicon-Vias,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV. view
  3. Woodrum, D. C., Zhang, X., Kotke, P. A., Joshi, Y. K., Fedorov, A. G., Bakir, M. S., and Sitaraman, S. K., “Reliability Assessment of Hydrofoil-Shaped Micro-Pin Fins,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV. view
  4. Zhang, X., Nasr, M. H., Woodrum, D. C., Green, C. E., Kotke, P. A., Sarvey, T. E., Joshi, Y. K., Sitaraman, S. K., Fedorov, A. G., Bakir, M., “Design, Microfabrication and Thermal Characterization of the Hotspot Cooler Testbed for Convective Boiling Experiments in Extreme-micro-gap with Integrated Micropin-fins and Great Loss Minimization,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV. view
  5. Asrar, P., Zhang, X., Woodrum, C., Green, C. E., Kotke, P. A., Sarvey, T. E., Sitaraman, S. K., Fedorov, A., Bakir, M., and Joshi, Y., “Flow Boiling of R245fa in a Micrograp with Integrated Staggered Pin Fins,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV. view
  6. Samet, D., Kwatra, A., and Sitaraman, S. K., “Compliance-Based Approach to Study Fatigue Crack Propagation for Copper-Epoxy Interface,” ASME - International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK2015) and the13th International Conference on Nanochannels, Microchannels and Minichannels (ICNMM), San Francisco, CA, July 2015, InterPackICNMM2015-48447. view
  7. Chen, W., Song, Y., Liang, J., and Sitaraman, S. K.,“Fabrication of Second-Level TriDelta Interconnects using Negative Dry-Film Photoresist”, Proceedings of the ASME 2014 International Mechanical Engineering Congress & Exposition (IMECE2014), November 2014, Montreal, Quebec, Canada, IMECE2014-40154. view
  8. Taylor, C. and Sitaraman, S. K., “Crowd Funding for Inspiring Graduate Students to Educate K12 Students about STEM,” ASME 2014 International Mechanical Engineering Congress and Exposition (IMECE2014), November 2014, Montreal, Canada, IMECE2014-40039. view
  9. Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S. K., “Cohesive Zone Models to Predict Multiple White Bumps in Flip-Chip Assemblies,” ASME 2014 International Mechanical Engineering Congress and Exposition (IMECE2014), November 2014, Montreal, Canada, IMECE2014-40199. view
  10. Chen, W., Song, Y., Liang, J., and Sitaraman, S. K., “Fabrication of Second-Level TriDelta Interconnects using Negative Dry-Film Photoresist,” ASME 2014 International Mechanical Engineering Congress and Exposition (IMECE2014), November 2014, Montreal, Canada, IMECE2014-40021. view
  11. Taylor, C., Liu, X., and Sitaraman, S. K., “Strain Monitoring near Through Silicon Vias through Metal Piezoresistive Sensors,” ASME 2014 International Mechanical Engineering Congress and Exposition (IMECE2014), November 2014, Montreal, Canada, IMECE2014-40041. view
  12. Raghavan, S., Schamdlak, I., Leal, G., and Sitaraman, S. K., “Framework to Extract Cohesive Zone Parameters Using Double Cantilever Beam and Four-Point Bend Fracture Tests,” 15th IEEE International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), April 2014, Ghent, Belgium view
  13. Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S., “Chip-Package Co-Design: Effect of Substrate Warpage on BEOL Reliability,”Proceedings of the ASME 2013 International Mechanical Engineering Congress and Exposition (IMECE2013), November 2013, San Diego, CA, IMECE2013-65877. view
  14. Liu, X., Simmons-Matthews, M., Wachtler, K. P., and Sitaraman, S. K., “Reliability Design of TSV in Free-Standing and 3D Integrated Packages,” Proceedings of the ASME 2011 International Mechanical Engineering Congress and Exposition (IMECE2011), November 2011, Denver, Colorado, IMECE2011-65767. view
  15. Jung, M., Liu, X., Sitaraman, S. K., Pan, D. Z., and Lim, S. K., “Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC,” International Conference on Computer-Aided Design, Nov. 2011 view
  16. Okereke, R., Kacker, K., and Sitaraman, S. K., “Parallel-Path Compliant Structures as Electrical Interconnects,” Proceedings of the ASME 2010 International Mechanical Engineering Congress and Exposition (IMECE2010), November 2010, Vancouver, British Columbia, Canada, IMECE2010-38376. view
  17. Liu, X., Chen, Q., Sundaram, V., Muthukumar, S., Tummala, R. R., and Sitaraman, S. K., “Reliable Design of Electroplated Copper Through Silicon Vias,” Proceedings of the ASME 2010 International Mechanical Engineering Congress and Exposition (IMECE2010), November 2010, Vancouver, British Columbia, Canada, IMECE2010-39283. view
  18. Zheng, J. and Sitaraman, S. K., “Interfacial fracture characterization of nano-scale thin films using single-strip stress-engineered superlayer,” IMECE2006-ASME, November 2006, Chicago, IL, USA, IMECE2006-13504. view
  19. Kacker K., Lo, G., and Sitaraman, S. K., “Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu ICs,” IMECE2006-ASME, November 2006, Chicago, IL, USA, IMECE2006-16014. view
  20. Mahalingam, S., Tonapi, S., Sitaraman, S., and Goray, K., “The characterization of Underfill-Passivation Interface under Monotonic and Fatigue Loading and its Application to Flip Chip Reliability Prediction,” Proceedings of IMECE2005, 2005 ASME International Mechanical Engineering Congress, November 2005, Orlando, Florida, USA, IMECE2005-83029. view
  21. Kim, I., Sitaraman, S., and Peak, R., “Reliability Objects Model: A Knowledge Model of System Design for Reliability,” Proceedings of IMECE2005, 2005 ASME International Mechanical Engineering Congress, November 2005, Orlando, Florida, USA, IMECE2005-79934. view
  22. Mahalingam, S., Tonapi, S., and Sitaraman, S., “A Fracture Mechanics Analyis of Underfill Delamination in Flip Chip Packages,” InterPACK ’05, The ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems, July 2005, San Francisco, CA, USA, IPACK2005-73493. view
  23. Zheng, J. and Sitaraman, S., “Single-Strip Decohesion Test to Characterize Nano-Scale Thin Film Delamination,” InterPACK ’05, The ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems, July 2005, San Francisco, CA, USA, IPACK2005-73495. view
  24. Bhattacharya, S., Varadarajan, M., Chahal, P., Lee, KJ, Bhattacharjee, A., Tummala, R., Sitaraman, S., Papapolymerou, J., Tentzeris, M., and Laskar, J.., “SOP Embedded Thin-Film Resistors on High and Low Loss Thick Film Dielectrics,” InterPACK ’05, The ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems, July 2005, San Francisco, CA, USA, IPACK2005-73500. view
  25. Zheng, J. and Sitaraman, S. K., “Superlayer Test for Interfacial Fracture Toughness Measurements,” Proceedings of IMECE2004, 2004 ASME International Mechanical Engineering Congress, November 13-19, 2004, Anaheim, California, USA, IMECE2004-61839. view
  26. Klein, K. and Sitaraman, S. K., “Compliant Stress-Engineered Interconnects for Next-Generation Packaging,” Proceedings of IMECE2004, 2004 ASME International Mechanical Engineering Congress, November 13-19, 2004, Anaheim, California, USA, IMECE2004-61990. view
  27. Hegde, S. and Sitaraman, S. K., " Thermo-Mechanical Evaluation of Embedded Optical Interconnects on Board," ITHERM’2004, The Nineth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Proceedings Vol. II, IEEE-CPMT, ASME, and IMAPS, June 2004, pp. 274-279. view
  28. Perkins, A. and Sitaraman, S. K., "Predictive Fatigue Life Equation for CBGA Electronic Packages based on Simple Design Parameters," ITHERM’2004, The Nineth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Proceedings Vol. II, IEEE-CPMT, ASME, and IMAPS, June 2004, pp. 253-258. view
  29. Zhu, Q., Ma, L., Lo, G., and Sitaraman, S. K., “Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Applications” Proceedings of IMECE’03, 2003 ASME International Mechanical Engineering Congress, November 15-21, 2003, Washington, DC, IMECE2003-41833. view
  30. Mahalingam, S., Hegde, S., Ramakrishna, G., Pucha, R. V., and Sitaraman, S. K., “Material Interaction Effects in the Reliability of High-Density Interconnect (HDI) Boards,” Proceedings of IMECE’03, 2003 ASME International Mechanical Engineering Congress, November 15-21, 2003, Washington, DC, IMECE2003-41645. view
  31. Ma, L., Zhu, Q., and Sitaraman, S K., “Contact Reliability of Innovative Compliant Interconnects for Next Generation Electronic Packaging,” Proceedings of IMECE’03, 2003 ASME International Mechanical Engineering Congress, November 15-21, 2003, Washington, DC, IMECE2003-41753. view
  32. Zhu, Q., Ma, L., and Sitaraman, S. K., “Electroplated Compliant Wafer-Level G-Helix Interconnect: A Solution to Future Electronic Packaging,” InterPACK’03, International Electronic Packaging Technical Conference and Exhibition, July 2003, InterPack2003-35342. view
  33. Modi, M. and Sitaraman, S. K., “Measurement of the Mode Mix Dependent Interfacial Fracture Toughness for a Ti/Si Interface using a Modified Decohesion Test,” InterPACK’03, International Electronic Packaging Technical Conference and Exhibition, July 2003, InterPack2003-35331. view
  34. Zhu, Q., Ma, L., and Sitaraman, S. K., “Design Optimization of One-Turn Helix – a Novel Compliant Off-Chip Interconnect," ITHERM’2002, The Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE-CPMT, ASME, and IMAPS, pp. 833-839. view
  35. Hegde, S., Pucha, R. V., Takahashi, A., and Sitaraman, S. K., "Thermomechanical Reliability of High Density Wiring Substrates," ITHERM’2002, The Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE-CPMT, ASME, and IMAPS, pp. 919-925. view
  36. Ramakrishna, G., Liu, F., and Sitaraman, S. K., "Experimental and Numerical Investigation of Microvia Reliability," ITHERM’2002, The Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE-CPMT, ASME, and IMAPS, pp. 932-939. view
  37. Zhu, Q., Ma, L and Sitaraman, S.K (2002). A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39679. view
  38. Kim, Y.K., Krondorfer, R and Sitaraman, S.K (2002). Process-Induced Stress Effect on Reliability of ChipSeal® Passivation Technology. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39681. view
  39. Ma, L., Zhu, Q and Sitaraman, S. K (2002). Mechanical and Electrical Study of Linear Spring and J-Spring. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39683. view
  40. Shan, Z and Sitaraman, S.K (2002). Characterization of Mechanical Properties of Thin Films by Nanoindentation Technique and Finite Element Simulation. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39668. view
  41. Modi, M.B and Sitaraman, S.K.(2002). Modified Decohesion Test (MDT) for Interfacial Fracture Toughness Measurement in Microelectronic/MEMS Applications. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39670. view
  42. Hegde, S., Pucha, R.V and Sitaraman, S.K. (2002). Enhanced reliability of high density wiring (HDW) substrates through new dielectric and base substrate materials. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39671. view
  43. Tunga, K., Pyland, J., Pucha, R.V and Sitaraman, S.K. (2002). Study on the choice of constitutive and fatigue models in solder joint life prediction. Proceedings of the ASME International Mechanical Engineering Congress and Exposition, November 17-22, 2002, New Orleans, LA, IMECE2002/EPP-39676. view
  44. Pucha, R. V., Ramakrishna, G., and Sitaraman, S. K., “Mechanics Issues at Micro-Scale Modeling of Electronic Packages,” Proceedings of 2001 ASME International Mechanical Engineering Congress and Exposition, Nov. 2001, New York, NY, IMECE2001/EPP-24709. view
  45. Ma, L., Zhu, Q., and Sitaraman, S., “Alternative Compliant Interconnects – Thermo-Mechanical Reliability, Design and Testing,” Proceedings of 2001 ASME International Mechanical Engineering Congress and Exposition, Nov. 2001, New York, NY, IMECE2001/EPP-24704. view
  46. Xie, W., Hu, H., and Sitaraman, S. K., “Determining Interfacial Delamination Propagation of ViaLuxTM 81/Copper Interface in Multilayered SOP Integrated Substrates,” InterPACK, July 2001, IPACK2001-15603. view
  47. Xie, W. and Sitaraman, S. K., “An Experimental Method for Determining the Critical Free-Edge Stress Intensity Factor (SIF),” InterPACK, July 2001, IPACK2001-15776. view
  48. Modi, M., Fork, D., and Sitaraman, S. K., “Numerical approximation of the energy release rate in intrinsically stressed Micro-Spring structures,” InterPACK, July 2001, IPACK2001-15605. view
  49. Ma, L., Zhu, Q., Modi, M., Sitaraman, S. K., Chua, C., and Fork, D., “Compliant Cantilevered Spring Interconnects for Flip-Chip Packaging,” InterPACK, July 2001, IPACK2001-15695. view
  50. Zhu, Q., Ma, L., and Sitaraman, S. K., “Mechanical and Preliminary Electrical Design of a Novel Compliant One-Turn Helix (OTH) Interconnect” InterPACK, July 2001, IPACK2001-15664. view
  51. Ahmad, M. and Sitaraman, S. K., “Contact Modeling of Flexible Micro-Spring Interconnects for High Performance Probing,” InterPACK, July 2001, IPACK2001-15697. view
  52. Bhattacharya, S. K., Sitaraman, S. K., Ume, I. C., Qu, J., Wong, C. P., Baldwin, D. F., and Tummala, R. R., “Large Area Processing Using Small Area Substrates: A Low-Cost MCM-D Thin Film Processing,” InterPACK, July 2001, IPACK2001-15527. view
  53. Raghunathan, R., Pucha, R. V., and Sitaraman, S. K., “Thermal Cycling Guidelines for Automotive, Computer, Portable, and Implantable Medical Device Applications,” 12th Symposium on Mechanics of SMT and Photonic Structures, Packaging of Electronic and Photonic Devices, ASME IMECE, EEP-Vol. 28, 2000, pp. 51-62. view
  54. Hu, H., Xie, W., and Sitaraman, S. K., “Interfacial Delamination Propagation in Multi-Layered High-Density Wiring Electronic Packaging Structures,” 12th Symposium on Mechanics of SMT and Photonic Structures, Packaging of Electronic and Photonic Devices, ASME IMECE, EEP-Vol. 28, 2000, pp. 103-111. view
  55. Raghunathan, R. and Sitaraman, S. K., "Qualification Guidelines for Automotive Packaging Devices," ITHERM’2000, The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Vol. I, IEEE-CPMT, ASME, IMAPS, and NIST, May 2000, pp. 385-392. view
  56. Xie, W. and Sitaraman, S. K., "Numerical Study of Interfacial Delamination in a System-on-Package (SOP) Integrated Substrate Under Thermal Loading" ITHERM’2000, The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Vol. II, IEEE-CPMT, ASME, IMAPS, and NIST, May 2000, pp. 356-361. view
  57. Hanna, C. E., Raghunathan, R., and Sitaraman, S. K., “Qualification Guidelines for Implantable Medical Devices,” ASME International Mechanical Engineering Congress and Exposition, Nashville, TN, Nov. 1999, 99-IMECE/EEP-27. view
  58. Variyam, M. and Sitaraman, S. K., “Design of Simulations Study of Multi-Layered Structures in Electronic Packaging,” Advances in Electronic Packaging, EEP-Vol. 26-2, InterPACK 99, ASME, June 1999, pp. 1665-1671. view
  59. Harries, R. J. and Sitaraman, S. K., “Numerical Study of Copper-Encapsulant Interfacial Delamination Propagation in a Peripheral Array Package,” Advances in Electronic Packaging, EEP-Vol. 26-2, InterPACK 99, ASME, June 1999, pp. 1755-1762. view
  60. Hanna, C. and Sitaraman, S. K., “Role of Underfill Materials and Thermal Cycling on Die Stresses,” Advances in Electronic Packaging, EEP-Vol. 26-1, InterPACK 99, ASME, June 1999, pp. 795-801. view
  61. Pang, J. H. L., Chong, Y. R., and Sitaraman, S. K., “FEA Modeling of FCOB Assembly Warpage and Stresses due to Underfill Encapsulation and Thermal Cycling Loading,” Advances in Electronic Packaging, EEP-Vol. 26-1, InterPACK 99, ASME, June 1999, pp. 803-807. view
  62. Sundararaman, V. and Sitaraman, S. K., “Experimental Characterization of Copper-Encapsulant Interfacial Fracture Toughness for a Peripheral Array Package,” Advances in Electronic Packaging, EEP-Vol. 26-2, InterPACK 99, ASME, June 1999, pp. 1881-1886. view
  63. Xie, W. and Sitaraman, S. K., “Analysis of Interlaminar Thermal Stresses in Unsymmetric Multi-Layered Electronic Assemblies and Packages,” Advances in Electronic Packaging, EEP-Vol. 26-2, InterPACK 99, ASME, June 1999, pp. 1155-1163. view
  64. Sundararaman, V., Harries, R. J., and Sitaraman, S. K., “Fracture-Mechanics Based Delamination Growth Prediction in the Very Small Peripheral Array Package,” 2nd Electronic Packaging Technology Conference, IEEE-CPMT/ASME/IMAPS, Dec 1998. view
  65. Harries, R. J. and Sitaraman, S. K., “Fracture-Mechanics-Based Delamination Growth Prediction in the VSPA Package – Numerical Simulation,” ASME International Mechanical Engineering Congress and Exposition, Anaheim, CA, Nov. 1998, 98-WA/EEP-10. view
  66. Sundararaman, V. and Sitaraman, S. K., “Fracture-Mechanics-Based Delamination Growth Prediction in the VSPA Package – Testing and Characterization,” ASME International Mechanical Engineering Congress and Exposition, Anaheim, CA, Nov. 1998, 98-WA/EEP-9. view
  67. Michaelides, S. and Sitaraman, S. K., “Effect of Material and Geometry Parameters on the Thermo-Mechanical Reliability of Flip-Chip Assemblies,” ITHERM’98, The Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE-CPMT, ASME, IMAPS, and NIST, Ed. S. H. Bhavnani, G. B. Kromann, and D. J. Nelson, May 1998, pp. 193-200. view
  68. Manjula, S. and Sitaraman, S. K., “Effect of Out-of-Plane Behavior on In-Plane Modeling,” ITHERM’98, The Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, IEEE-CPMT, ASME, IMAPS, and NIST, Ed. S. H. Bhavnani, G. B. Kromann, and D. J. Nelson, May 1998, pp. 256-262. view
  69. Harries, R. and Sitaraman, S. K., “Process Modeling and Interfacial Behavior in the VSPA Package,” MD-Vol. 80, Composites and Functionally Graded Materials, ASME 1997, pp. 293-299. view
  70. R. C. Dunne, Smith, K. and Sitaraman, S. K., “Thermo-Mechanical Behavior of Vias in HDI Structures,” Advances in Electronic Packaging 1997, EEP-Vol. 19-2, ASME, Ed. E. Suhir, Y. C. Lee, M. Shiratori, and G. Subbarayan, pp. 1305-1311. view
  71. Michaelides, S. and Sitaraman, S. K, “Role of Underfilling Imperfections on Flip-Chip Reliability,” Advances in Electronic Packaging 1997, EEP-Vol. 19-2, ASME, Ed. E. Suhir, Y. C. Lee, M. Shiratori, and G. Subbarayan, pp. 1487-1493. view
  72. Peak, R. S., Fulton, R. E., and Sitaraman, S. K., “Thermomechanical CAD/CAE Integration in the TIGER PWA Toolset,” Advances in Electronic Packaging 1997, EEP-Vol. 19-2, ASME, Ed. E. Suhir, Y. C. Lee, M. Shiratori, and G. Subbarayan, pp. 957-969. view
  73. Sundararaman, V. and Sitaraman, S. K., “Interfacial Fracture Toughness Determination for Reliable Design of Multi-Layered Structures,” 97-WA/EEP-1, 9th Symposium on Mechanics of Surface Mount Assembly, ASME International Mechanical Congress and Exposition, Dallas, TX, Nov. 1997. view
  74. Baldwin, D. F., Beerensson, J. T., and Sitaraman, S. K., “Thermal Management in Direct Chip Attach Assemblies,” Sensing, Modeling, and Simulation in Emerging Electronic Packaging Interconnects, Ed. C. Ume, C.-P. Yeh, and K. Chiang, ASME International Mechanical Engineering Congress, Atlanta, Nov. 1996, pp. 29-37. view
  75. Murphy, R. S. and Sitaraman, S. K., “Thermal Fatigue Life of the VSPA Package Solder Joints”, 8th Symposium on Mechanics of Surface Mount Assemblies, 96-WA/EEP-13, ASME International Mechanical Engineering Congress, Atlanta, Nov. 1996. view
  76. Dunne, R. C. and Sitaraman, S. K., “Warpage and Stress-Strain Distribution in a Sandwich Substrate with Integrated Passives”, 8th Symposium on Mechanics of Surface Mount Assemblies, 96-WA/EEP-6, ASME International Mechanical Engineering Congress, Atlanta, Nov. 1996. view
  77. Sizemore, J. and Sitaraman, S. K., “Elastic-Plastic and Elastic-Viscoplastic Modeling of Plated-Through Holes in Solder Shock Test,” HTD-Vol. 319/EEP-Vol. 15, Cooling and Thermal Design of Electronic Systems, Ed. C. H. Amon, ASME International Mechanical Engineering Congress and Exposition, Nov. 12-17, 1995, San Francisco, CA, pp. 163-173. view
  78. Sitaraman, S. K., Kinzel, G. L., and Altan, T., "Rigid-Plastic Analysis of Sheet Metal Stretching," Computer-Aided Design and Manufacture of Dies and Molds, Ed. K. Srinivasan and W. R. Devries, ASME Winter Annual Meeting, Chicago, Illinois, Nov. 28 - Dec. 2, 1988, pp. 167-183. view
  79. Sitaraman, S. K., Kinzel, G. L., and Altan, T., "A Computer-Aided Design System for Process Sequence in Axisymmetric Sheet Metal Forming," Proceedings of the Near Net Shape Manufacturing Conference, Ed. P. W. Lee and B. L. Ferguson, ASM International, Columbus, Ohio, Nov. 8 -10, 1988, pp. 97-105. view

ECTC/Other

  1. Samet, D., Rambhatla, V. N. N. Trilochan,, and Sitaraman, S.K, “Mode Mixity Dependency on Fatigue Crack Propagation for an Epoxy molding Compound/Copper Interface”, TECHCON, Austin, TX, Sep. 2017 view
  2. V. N. N. T. Rambhatla, D. Samet, P. M. Raj, S. Kawamoto, R. R. Tummala and S. K. Sitaraman, "Interfacial Delamanination of Mold Compound in Fan-Out Packages," 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, FL, 2017, pp. 827-833. view
  3. McCann, S., Kuramochi, S., Yun, H, Sundaram, V., Pulugurtha, M. R., Tummala, R. R, and Sitaraman, S. K., “Board-Level Reliability of 3D Through Glass Via Filters During Thermal Cycling,” 66th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2016. view
  4. Samet, D., Kwatra, A., and Sitaraman, S. K., “Cohesive Zone Parameters for a Cyclically Loaded Copper-Epoxy Interface,” 66th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2016. view
  5. McCann, S.R.; Sato, Y.; Sundaram, V.; Tummala, R.R.; Sitaraman, S.K., "Study of cracking of thin glass interposers intended for microelectronic packaging substrates," Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th , vol., no., pp.1938,1944, 26-29 May 2015 view
  6. Woodrum, D.C.; Sarvey, T.; Bakir, M.S.; Sitaraman, S.K., "Reliability study of micro-pin fin array for on-chip cooling," Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th , vol., no., pp.2283,2287, 26-29 May 2015 view
  7. Kwatra, A.; Samet, D.; Sitaraman, S.K., "Effect of thermal aging on cohesive zone models to study copper leadframe/mold compound interfacial delamination," Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th , vol., no., pp.1531,1537, 26-29 May 2015 view
  8. Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S. K., “Cohesive Zone Model-Based Design Guidelines Against White Bump Failures,” TECHCON, Austin, TX, Sep. 2014 view
  9. McCann, S.R.; Sundaram, V.; Tummala, R.R.; Sitaraman, S.K., "Flip-chip on glass (FCOG) package for low warpage," Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th , vol., no., pp.2189,2193, 27-30 May 2014 view
  10. Krieger, W.E.R.; Raghavan, S.; Kwatra, A.; Sitaraman, S.K., "Cohesive zone experiments for copper/mold compound delamination," Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th , vol., no., pp.983,989, 27-30 May 2014 view
  11. Tian, Y., Liu, X., Chow, J., Wu, Y. P., and Sitaraman, S. K., “Comparison of IMC Growth in Flip-Chip Assemblies with 100- and 200-µm-Pitch SAC305 Solder Joints,” 63rd Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2013, pp. 1005-1009. view
  12. Chen, W., Bhat, A., and Sitaraman, S. K., “Use of Compliant Interconnects for Drop Impact Isolation,” 63rd Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2013, pp. 835-839 view
  13. Okereke, R. and Sitaraman, S. K., “Three-Path Electroplated Copper Compliant Interconnects: Fabrication and Modeling Studies,” 63rd Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2013, pp. 129-135. view
  14. Xu, J., Razeeb, K. M., Sitaraman, S. K., and Mathewson, A., “The Fabrication of Ultra Long Metal Nanowire Bumps and their Application as Interconnects,” 12th IEEE International Conference on Nanotechnology (IEEE-NANO), Birmingham, UK, August 2012. view
  15. Taylor, C. and Sitaraman, S. K., “In-Situ Strain Measurement with Metallic Thin Film Sensors,” 62nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May-June 2012, pp. 641-646. view
  16. Raghavan, S., Schmadlak, I., and Sitaraman, S. K., “Interlayer Dielectric Cracking in Back End of Line (BEOL) Stack,” 62nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May-June 2012, pp. 1467-1474. view
  17. Liu, X., Li, M., Mullen, D., Cline, J., and Sitaraman, S. K., “Design and Assembly of a Double-Sided 3D Package with a Controller and a DRAM Stack,” 62nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May-June 2012, pp. 1205-1212. view
  18. Lee, R.E., Okereke, R., and Sitaraman, S.K., "Multi-path Fan Shaped Compliant Off-chip Interconnects," 61st Electronic Components and Technology Conference, IEEE-CPMT and EIA, Lake Buena Vista, FL, May-June 2011, pp. 2141-2145. view
  19. Liu, X., Chen, Q., Sundaram, V., Simmons-Matthews, M., Wachtler, K.P., Tummala, R.R., and Sitaraman, S.K., "Thermo-mechanical Behavior of Through Silicon Vias in a 3D Integrated Package with Inter-chip Microbumps," 61st Electronic Components and Technology Conference, IEEE-CPMT and EIA, Lake Buena Vista, FL, May-June 2011, pp. 1190-1195. view
  20. Ostrowicki, G. and Sitaraman, S. K., “Interfacial Fracture Characterization of Thin Films through Magnetic Actuation,” Proceedings of the NSF Civil, Mechanical, and Manufacturing Innovation Division, Research and Innovation Conference, Atlanta, GA, January 2011. view
  21. Ostrowicki, G., Zheng, J., and Sitaraman, S. K., “Non-Contact Experimental Technique to Characterize Interfacial Crack Propagation in Nano-Scale and Micro-Scale Thin Films,” Proceedings of the NSF Civil, Mechanical, and Manufacturing Innovation Division, Research and Innovation Conference, Honolulu, HI, June 2009. view
  22. Liu, X., Chen, Q., Dixit, P., Chatterjee, R., Tummala, R. R., and Sitaraman, S. K., “Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV),” 59th Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2009, pp. 624 – 629. view
  23. Perkins, A. and Sitaraman, S. K., “A Study into the Sequencing of Thermal Cycling and Vibration Tests,” 58th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2008, pp. 584-592. view
  24. Perkins, A. and Sitaraman, S.K. "Unified Finite Element Model for Prediction of Solder Joint Fatigue Under Thermal, Power, and Vibration Environments for Ceramic Area Array Electronic Packages," 2007 Surface Mount Technology Association International (SMTAI) Conference Proceedings, Orlando, FL, Oct. 2007, p. 460-478. view
  25. Kacker, K., Sokol, T., and Sitaraman, S. K., “FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects,” 57th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Reno, NV, May 2007, pp. 1678-1684. view
  26. Kim, I., Pucha, R. V., Peak, R. S., and Sitaraman, S. K., “System-Design-for-Reliability Tools for Highly Integrated Electronic Packaging Systems,” 57th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Reno, NV, May 2007, pp. 1809-1814. view
  27. Kumbhat, N., Raj, P. M., Pucha, R. V., Sundaram, V., Bongio, E., Sitaraman, S., and Tummala, R. R., “A Novel Low CTE, High Stiffness Ceramic Composite Core,” Circuits Assembly, January 2007, p. 28. view
  28. Zheng, J. and Sitaraman, S. K., “Fixtureless Superlayer-Driven Decohesion Test for Interfacial Fracture Toughness Measurement of Nano-Scale Thin Films,” Thin Films and Intefaces-4, International Conference on Advanced Materials Design and Development, Goa, India, Dec. 2005. view
  29. Lee, K.J., Pucha, R., Varadarajan, M., Bhattacharya, S., Tummala, R., and Sitaraman, S.K., "Reliability Assessment of Embedded Capacitors in Multilayered Microvia Organic Substrate," IMAPS 2005, Philadelphia, PA, Sep. 2005. view
  30. Perkins, A. and Sitaraman, S. K., "Acceleration Factor to Relate Thermal Cycles to Power Cycles for Ceramic Area Array Packages,” 2005 Surface Mount Technology Association International (SMTAI) Conference Proceedings, Chicago, Sep. 2005. view
  31. Kacker, K., Lo, G., and Sitaraman, S. K., "Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects," 55th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2005, pp. 545-550. view
  32. Klein, K.M., Zheng, J., Gewirtz, A., Sarma, D. S. R., Rajalakshmi, S., and Sitaraman, S.K., "Array of Nano-Cantilevers as a Bio-Assay for Cancer Diagnosis," ," 55th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2005, pp. 583-587. view
  33. Kumbhat, N., Raj, P. M., Pucha, R. V., Atmur, S., Doraiswamy, R., Sundaram, V., Bhattacharya, S., Sitaraman, S.K., and Tummala, R. "Recent Advances in Composite Substrate Materials for High-Density and High-Reliability Packaging Applications," ," 55th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2005, pp. 1364-1372. view
  34. Zheng, J., Klein, K.M., Pucha, R., Sitaraman, S.V. , Merlin, D., Rajalakshmi, S., Sarma, D. S. R., Gewirtz, A. and Sitaraman, S.K., "Nano-Cantilevers for an Ultra-Sensitive Bio-Assay," Proceedings of NSTI Nanotechnology Conf. and Trade Show, Vol. 1 Chapter 8: Bio Micro Sensors, May 2005, pp. 406-409. view
  35. Lee, K.J., Bhattacharya, S., Varadarajan, M., Wan, L., Abothu, I.R., Sundaram, V., Muthana, P., Balaraman, D., Raj, P.M., Swaminathan, M., Sitaraman, S.K. and Tummala, R.R., “Design, Fabrication, and Reliability Assessment of Embedded Resistors and Capacitors on Multilayered Microvia Organic Substrates,” Proceedings of the IEEE-CPMT International Symposium and Exhibition on Advanced Packaging Materials, Irvine, CA, pp. 249-254, March 16-18, 2005. view
  36. Pucha, R.V., Sitaraman, S.K., Hegde, S., Damani, M., Wong, C.P., Qu, J., Zhang, Z., Raj, P.M., Tummala, R.R., “Materials and mechanics challenges in SOP-based convergent Microsystems,” Micromaterials and Nanomaterials, A publication series of the Micro Materials Center Berlin at the Fraunhofer Institute IZM, Issue No. 3, 2004, pp.16-29 (invited). view
  37. N. Kumbhat, P. Markondeya Raj, S. Hegde, R.V. Pucha, V. Sundaram, S. Hayes, S. Atmur, S. Bhattacharya, S.K. Sitaraman, and R.R. Tummala, "Novel Board Material Technology for Next-Generation Microelectronic Packaging" in Developments in Dielectric Materials and Electronic Devices, Ceramic Transactions (K.M.Nair et al, Editors), Vol.167, 2004, pp. 371-382. view
  38. Zheng, J. and Sitaraman, S. K., “Stress-Engineered Single-Strip Decohesion Test for the Measurement of Interfacial Fracture Toughness,” Damage Tolerant Design and Materials, Chennai, India, December 16-18, 2004, pp. 1-6 (invited). view
  39. Damani, M., Pucha, R.V., Bhattacharya, S., Tummala, R., and Sitaraman, S.K., "Physics-based Reliability Assessment of Embedded Passives," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 2027-2031 view
  40. Kumbhat, N., Raj, P.M., Pucha, R.V., Sundaram, V., Doraiswami, R., Bhattacharya, S., Hayes, S., Atmur, S., Sitaraman, S.K., and Tummala, R., "Next Generation of Package/Board Materials Technology for Ultra-High Density Wiring and Fine-Pitch Reliable Interconnection Assembly," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 1843-1850 view
  41. Mahalingam, S., Hegde, S., Ahmad, J., Pucha, R.V., Sundaram, V., Liu, F., White, G., Tummala, R., and Sitaraman, S.K., "Materials, Processes and Reliability of Mixed-Signal Substrates for SOP Technology," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 1630-1635 view
  42. Tunga, K., Kacker, K., Pucha, R.V., and Sitaraman, S.K., "Accelerated Thermal Cycling: Is it Different for Lead-free Solder?," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 1579-1585 view
  43. Kim, W., Madhavan, R., Mao, J., Choi, J., Choi, S., Ravi, D., Sundaram, V., Sankararaman, S. , Gupta, P., Zhang, Z., Lo, G., Swaminathan, M., Tummala, R., Sitaraman, S.K., Wong, C.P., Lyer, G., Rotaru, G., and Tay, A., "Effect of Wafer Level Packaging, Silicon Substrate and Board Material on Gigabit Board-Silicon-Board Data Transmission," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 1506-1512 view
  44. Perkins, A., and Sitaraman, S.K., "Vibration-Induced Solder Joint Failure of a Ceramic Column Grid Array (CCGA) Package," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 1271-1278 view
  45. Hegde, S., Pucha, R.V., Guidotti, D., Liu, F., Chang, Y.J., Tummala, R., Chang, G. and Sitaraman, S. K., "Design, Fabrication, and Reliability Testing of Embedded Optical Interconnects on Package," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 895-900 view
  46. Zhang, Z., Fan, L., Sitaraman, S. K., and Wong, C.P. "Four-Laser Bending Beam Measurements and FEM Modeling of Underfill Induced Wafer Warpage," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 747-753 view
  47. Lo, G. and Sitaraman, S. K., "G-Helix: Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 320-325 view
  48. Zheng, J. and Sitaraman, S. K., "In-Process Measurement of the Interfacial Fracture Toughness for a Sub-micron Titanium Thin Film and Silicon Interface using a Single-Strip Decohesion Test," 54th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, June 2004, pp. 134-139. view
  49. Modi, M. and Sitaraman, S. K., “Single-Substrate Decohesion Test for Interfacial Fracture Toughness Measurement,” EPTC 2003, 5th Electronics Packaging Technology Conference, Proceedings EPTC 2003, 5th Electronics Packaging Technology Conference, IEEE-CPMT and IMAPS, Dec. 10-12, 2003, Singapore, pp. 456-461. view
  50. Classe, F. and Sitaraman, S. K., “Asymmetric Accelerated Thermal Cycles: An Alternative Approach to Accelerated Reliability Assessment of Microelectronic Packages,” Proceedings of EPTC 2003, 5th Electronics Packaging Technology Conference, IEEE-CPMT and IMAPS, Dec. 10-12, 2003, Singapore, pp. 81-89. view
  51. Kim, W, Madhavan, R., Mao, J., Choi, J., Choi, S., Ravi, D., Sundaram, V., Sankararaman, S., Gupta, P., Zhang, Z., Lo, G., Swaminathan, M., Tummala, R. R., Sitaraman, S., Wong, C. P., Iyer, M. K., Rotaru, M., and Tay, A. A. O., “Electrical Design of Wafer Level Package on Board for Gigabit Data Transmission,” Proceedings of EPTC 2003, 5th Electronics Packaging Technology Conference, IEEE-CPMT and IMAPS, Dec. 10-12, 2003, Singapore, pp. 150-159. view
  52. Perkins, A., and Sitaraman, S.K. “Thermo-Mechanical Failure Comparison and Evaluation of CCGA and CBGA Electronic Packages,” 53nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, New Orleans, LA, May 2003, pp. 422-430. view
  53. Tunga, K., Pyland, J., Pucha, R. V., and Sitaraman, S.K. “Field-Use Conditions Vs. Thermal Cycles – A Physics-Based Mapping Study,” 53nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, New Orleans, LA, May 2003, pp. 182-188. view
  54. Zhang, Z., Vorakunpinij, A., Sitaraman, S.K., and Wong, C. P., “Time Evolution of Temperature Distribution of a Flip-Chip No-Flow Underfill Package during Solder Reflow Process ,” 53nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, New Orleans, LA, May 2003, pp. 443-451. view
  55. Ramakrishna, G., Liu , F., and Sitaraman, S.K. “Role of Substrate and Dielectric Materials on the Thermo mechanical Reliability of Microvias,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 439-445. view
  56. Hegde, S., Pucha, R.V., and Sitaraman, S.K. “ Selection of Optimal Materials and Geometry for Reliability of High Density Wiring (HDW) Substrates,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 446-451. view
  57. Modi, M. and Sitaraman, S.K. “Effect of Adhesive Layer Properties on Fracture in Thin Film High Density Interconnects,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 847-853. view
  58. Zhu, Q., Ma, L. and Sitaraman, S.K. “Design and Optimization of a Novel Compliant Off-Chip Interconnect – One-Turn Helix,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 910-914. view
  59. Hu, H. and Sitaraman, S.K. “ Optimal Design of an Integrated Substrate Based On the Analysis of Warpage and Delamination,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 941-946. view
  60. Ramakrishna, G., Pucha, R.V., and Sitaraman, S.K. “ Micro-scale Plasticity Effects in Microvia Reliability Analysis,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 1304-1309. view
  61. Ma, L., Qi, Z., Hantschel, T., Fork, D. K., and Sitaraman, S.K. “J-Springs - Innovative Compliant Interconnects for Next-Generation Packaging,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 1359-1365. view
  62. Ahmad, J. and Sitaraman, S. K., “Modeling Methodologies to Study PWB Assembly Reliability,” 52nd Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, May 2002, pp. 1658-1664. view
  63. Zhu, Q., Ma, L., and Sitaraman, S. K. “Lithography-Based One-Turn Helix (OTH) Compliant Interconnects for Wafer Level Packaging,” International Workshop On Wafer Level CSP and Flip Chip Packaging, Stone Mountain, GA, March 2002 view
  64. Pyland, J., Pucha, R., and Sitaraman, S. K., “Effect of Underfill on BGA Reliability,” 51st Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2001, pp. 85-90 view
  65. Xie, W., Hu, H., and Sitaraman, S. K., “Selection of Base Substrate Material for Design Against Interfacial Delamination for a Multilayered SOP Structure,” 51st Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, May 2001, pp. 613-619. view
  66. Fork, D. K., Chua, C. L., Wong, L., Alimonda, A. S., Smith, D. L., Modi, M., Zhu, Q., Ma, L., and Sitaraman, S. K., “Stress-engineered metal interconnects”, Proceeding of 2001 International Conference on High-Density Interconnect and System Packaging, Santa Clara, CA, USA, April, 2001. view
  67. Ma, L., Zhu, Q., Sitaraman, S. K., Chua, C., and Fork D. K., “Novel Nanospring Interconnects for High-Density Applications,” 7th International Symposium and Exhibition on Advanced Packaging Materials - Processes, Properties, and Interfaces, IMAPS-IEEE, Braselton, GA, March 2001, pp. 372-378. view
  68. Sitaraman, S. K., Dunne, R. C., Raghunathan, R., and Xie, W., “Implantable Medical Devices and Next-Genertion Microsystems Packaging: An Integrated Process Modeling Approach to High Reliability and Miniaturization,” NSF Design and Manufacturing Grantees Conference, Tampa, FL, Jan. 7-10, 2001. view
  69. Chua, C. L., Fork, D. K., Smith, D. L., McIntyre, H., Ma, L., Zhu, Q., Modi, M. and Sitaraman, S. K., “High density packaging of vertical-cavity surface-emitting laser arrays using micro-machined spring arrays”, Proceedings of IEEE Lasers and Electro-Optics Society (LEOS) 2000 Annual Meeting, Rio Grande, Puerto Rico, November 2000. view
  70. Bhattacharya, S., Baldwin, D., Sitaraman, S., Qu, J., Wong, C. P., Ume, I. C., and Tummala, R. R., "Low Cost MCM: Large Area Packaging using Small Area Substrates, Part 2,” High-Density Interconnect International, October 2000, pp. 36-39. view
  71. Fork, D. K., Chua, C. L., Kim, P., Romano, L. T., Lau, R., Wong, L., Alimonda, A., Gelaz, V., Teepe, M., Haemer, J., Modi, M., Zhu, Q., Ma, L., Sitaraman, S. K., Smith, D. L., and Mok, S., “Nano-spring arrays for high density interconnect”, Proceeding of International Optical Engineering Society (SPIE), Micromachined Devices and Components VI, Santa Clara, CA, USA, September, 2000 (invited). view
  72. Bhattacharya, S., Baldwin, D., Sitaraman, S., Qu, J., Wong, C. P., Ume, I. C., and Tummala, R. R., "Low Cost MCM: Large Area Packaging using Small Area Substrates, Part 1,” High-Density Interconnect International, September, 2000, pp. 20-25. view
  73. Schubert, A., Dudek, R., Leutenbauer, R., Coskina, P., Becker, K. –F., Kloeser, H., Reichl, D., Baldwin, D., Qu, J., Swaminathan, M., Wong, C. P., Tummala, R., and Sitaraman, S. K., “Numerical and Experimental Investigation of Large IC Flip Chip Attach,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1338-1346. view
  74. Haemer, J. M., Sitaraman, S. K., Fork, D. K., Smith, D., Mok, S., and Chong, F. C., “Flexible Micro-Spring Interconnects for High Performance Probing,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1157-1163. view
  75. Paydenkar, C. S., Baldwin, D. F., Sitaraman, S., Wong, C. P., and Lewis, B. J., “Chip Scale Polymer Stud Grid Array Packaging and Reliability Based on Low Cost Flip-Chip Processing,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1449-1459. view
  76. Hu, H., Xie, W., and Sitaraman, S. K., “Analytical Model to Study Interfacial Delamination Propagation in a Multi-Layered Electronic Packaging Structure under Thermal Loading,” 50th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Las Vegas, NV, May 2000, pp. 1526-1534. view
  77. Sitaraman, S. K., Xie, W., Sundararaman, V., and Harries, R. J., “Application of Fracture Mechanics for Next-Generation Packaging Structures,” Micro Materials, MicroMat 2000, Sponsored by IEEE, ASME, IMAPS, Fraunhofer Society for Applied Sciences, German Society for Materials Research and Testing, Berlin, Germany, April 2000 (invited). view
  78. Dunne, R. C., Sitaraman, S. K., Luo, S., Wong, C. P., Estes, W. E., and Periyasamy, M., “Cure Kinetics Modeling of ViaLux 81: A Novel Epoxy Photo-Dielectric Film (PDDF) for Microvia Applications,” 6th International Symposium and Exhibition on Advanced Packaging Materials - Processes, Properties, and Interfaces, IMAPS-IEEE, Braselton, GA, March 2000, pp. 254-260. view
  79. Sitaraman, S. K., Dunne, R. C., Hanna, C. E., Michaelides, S., Raghunathan, R., and Xie, W., “An Integrated Process-Mechanics and Reliability Prediction Methodology for Implantable Medical Devices,” NSF Design and Manufacturing Grantees Conference, Vancouver, BC, Canada, Jan. 4-6, 2000. view
  80. Raghunathan, R., Hanna, C., and Sitaraman, S. K., “Qualification Guidelines for Implantable Devices and Automotive Applications,” Proceedings of Symposium on Advances in Electronics Packaging, APACK’99, Singapore, December 1999, pp. 446-453 (invited). view
  81. Hanna, C. E., Raghunathan, R., and Sitaraman, S. K., “Qualification Guidelines for Implantable Medical Devices,” The Second IEEE International Symposium on Polymeric Electronics Packaging, PEP’99, Gothenburg, Sweden, Oct. 1999, pp. 185-197 (invited). view
  82. Dunne, R. C., Sitaraman, S. K., Rao, Y., Luo, S., Wong, C. P., Estes, W. E., Gonzalez, C. G., Murray, E. B., Overcash, T. R., Anderson, R. E., Coburn, J. C., and Periyasamy, M., “Cure Optimization and Process Guidelines for a Novel Epoxy Photo-Dielectric Dry Film for Microvia Applications,” 8th Electronic Circuits World Convention, Tokyo, September 1999. view
  83. Hanna, C., Michaelides, S., Palaniappan, P., Baldwin, D., and Sitaraman, S. K., “Numerical and Experimental Study of the Evolution of Stresses in Flip-Chip Assemblies during Assembly and Thermal Cycling,” 49th Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, June 1999, pp. 1001-1009. view
  84. Variyam, M. and Sitaraman, S. K., “Palletized Approach to Large-Area Thin-Film Processing - Materials, Models, and Measurement,” 49th Electronic Components and Technology Conference, IEEE-CPMT and EIA, San Diego, CA, June 1999, pp. 686-693. view
  85. Manjula, S., Sundararaman, V., Sitaraman, S. K., Wong, C. P., Wu, J., and Pike, R. T., “Multi-Layered Structure: Adhesive Selection and Process Mechanics,” 5th International Symposium and Exhibition on Advanced Packaging Materials - Processes, Properties, and Interfaces, IMAPS-IEEE, Braselton, GA, March 1999, pp. 48-52. view
  86. Sitaraman, S. K., “Implantable Medical Devices: A Process-Modeling Approach to High Reliability and Miniaturization,” NSF Design and Manufacturing Grantees Conference, Long Beach, CA, Jan. 5-8, 1999. view
  87. Dunne, R. C. and Sitaraman, S. K., “Process Modeling of Sequential Build-Up of Multilayered Structures,” 48th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Seattle, WA, May 1998, pp. 353-361. view
  88. Sitaraman, S. K., Sundararaman, V., Manjula, S., Wong, C. P., Lu, D., Pike, R. T., Meyers, L., “Use of Highly Compliant Adhesives in the Large Area Processing of MCM-D Substrates,” 48th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Seattle, WA, May 1998, pp. 895-899. view
  89. Pang, H. L. J., Tan, T., and Sitaraman, S. K. “Thermo-Mechanical Analysis of Solder Joint Fatigue and Creep in a Flip Chip on Board Package Subjected to Temperature Cycling Loading,” 48th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Seattle, WA, May 1998, pp. 878-883. view
  90. Dunne, R. C. and Sitaraman, S. K., “Sequential Process Modeling of SLIM Substrate Fabrication,” 4th International Symposium and Exhibition on Advanced Packaging Materials - Processes, Properties, and Interfaces, IMAPS-IEEE, Braselton, GA, March 1998, pp. 175-182. view
  91. Pang, H. L. J., Sitaraman, S. K., Zwemer, D. A., and Hassell, P., “Thermally-Induced Warpage and Stresses in Flip-Chip on Board (FCOB) Assembly”, 2nd International Advanced Technology Workshop on Flip Chip Technology, IMAPS-IEEE, March 14-16, 1998, Braselton, GA. view
  92. Ramani, K. and Sitaraman, S. K., “Dissimilar Material Systems: Manufacturing Processes, Design, and Mechanics,” MD-Vol. 80, Composites and Functionally Graded Materials, ASME 1997, p. 277. view
  93. Tummala, R., Swaminathan, M., and Sitaraman, S. K., Next-Generation Package Design, IMAPS Advanced Technology Workshop, June 1997. view
  94. Murphy, R. S. and Sitaraman, S. K., “Two and Three-Dimensional Modeling of VSPA Butt Solder Joints”, 47th Electronic Components and Technology Conference, IEEE and EIA , San Jose, CA, May 18-21, 1997, pp. 472-478. view
  95. Dunne, R. C. and Sitaraman, S. K., “The Effect of Substrate Materials on the Thermal Mechanical Behavior of Multilayer Structures, 3rd International Symposium and Exhibition on Advanced Packaging Materials - Processes, Properties, and Interfaces, IMAPS-IEEE, Braselton, GA, March 9-12, 1997, pp. 134-137. view
  96. Wong, C. P., Tummala, R., Qu, J., and Sitaraman, S., “Microelectronic Package Trends - The Role of Reliability in Particular, Related to Solder Joints,” Design and Reliability of Solder and Solder Interconnections, Ed. R. K. Mahidhara, D. R. Frear, S. M. L. Sastry, K. L. Murty, P. K. Liaw, and W. L. Winterbottom, The Minerals, Metals, and Materials Society, Orlando, FL, Feb. 1997, pp. 3-8 (invited). view
  97. Dunne, R. C. and Sitaraman, S. K., “Thermo-Mechanical Reliability of a ‘Sandwich’ Substrate with Integrated Passives”, VIII International Congress on Experimental Mechanics and Experimental/Numerical Mechanics in Electronics Packaging, Nashville, TN, June 10-13, 1996, pp. 19-20. view
  98. Michaelides, S., and Sitaraman, S. K., “Micro-Macro-Micro Modeling in Electronic Packaging,” Experimental/Numerical Mechanics in Electronic Packaging, VIII International Congress on Experimental Mechanics, June 10-13, 1996, Nashville, TN, pp. 44-45. view
  99. Dunne, R. C. and Sitaraman, S. K., “Thermo-Mechanical Modeling of a Novel MCM-DL Technology,” 46th Electronic Components and Technology Conference, IEEE and EIA, Orlando, Florida, May 1996, pp. 815-820. view
  100. Michaelides, S., and Sitaraman, S. K., “Thermo-Mechanical Design of Flip-Chip for Harsh Environments,” ISHM International Conference and Exhibition on Multichip Modules, April 17-19, 1996, Denver, CO, pp. 155-160. view
  101. Sitaraman, S. and Tavoularis, S., “Mean Flow Measurements in Rod Bundle Subchannels,” Proc. of the 10th Canadian Congress on Applied Mechanics, The University of Western Ontario, London, ON, June 2-7, 1985, pp. B197-B198. view