The focus of this project is to design, fabricate, assemble, characterize, and test several innovative compliant, free-standing, off-chip or off-substrate interconnects that are optimized for electrical, thermal, and mechanical performance and that are scalable, cost-effective, environmentally-friendly, and reworkable. The compliant interconnects can be fabricated on large wafers or large substrates to function as first-level or second-level interconnects.Several approaches are being currently pursued, and each approach has its relative strengths make it more suited to a certain class of applications over others. The three main approaches currently being pursued are Single-path compliant interconnects, Multi-path compliant interconnects, and Compliant Z-axis interconnects.
Compliant Interconnect Snapshots
- Compliant Interconnect
- Electroplated Compliant Off-Chip Interconnects
- Stress-Gradient Based Compliant Interconnects