The continued miniaturization in combination with enhanced performance in the microelectronics industry calls for innovative ways to stack IC dies and create three-dimensional microelectronic packages. Through silicon vias (TSVs) are being pursuded aggressively by microelectronics industry to facilitate 3D microsystems. This project aims to understand the thermo-mechanical reliability of TSVs through fabrication and thermal cycling as well as through finite-element simulations. The behavior of TSVs in stand-alone wafers and in packaged stacked dies is being studied. In addition, nano- and micro-scale sensors are also fabricated close to the TSVs to experimentally measure the stresses near the TSVs.