Reduction in first-level and second-level interconnect pitch calls for multiple layers on the substrate and the board with aggressive traces and space as well as microvias. To reduce cost and to facilitate large-area processing, organic substrates/boards with sequential interlayer processing are being pursued in the microsystems industry. Under such sequential processing, it is necessary to understand the warpage of the substrate with each process step so that yield issues associated with misregistration can be effectively addressed. Also, the warpage studies will be helpful to understand assembly yield issues as well as first- and second-level interconnect reliability. CASPaR projects focus on large-area substrate warpage prediction during various process and assembly steps with and without trace pattern image analysis, with and without viscoelastic relaxation of interlayer dielectric, and with and without the cure kinetics of interlayer dielectrics. Techniques and process recipes are also explored to reduce the overall warpage.
- Physics-Based Reliability of Dielectrics on Alternate Base Substrates
- Cure-Kinetics Modeling for Next-Generation Interlayer Dielectrics
- An Integrated Process Modeling Methodology for Sequential Multilayered Integrated SOP Substrate Fabrication
- Physics-Based Thermo-Mechanical Reliability of Microvias