Thermal Annealing Effects on Copper Microstructure in Through–Silicon-Vias

Citation: 
Song, Y., Abbaspour, R., Bakir, M., and Sitaraman, S. K., “Thermal Annealing Effects on Copper Microstructure in Through–Silicon-Vias,” ITHERM 2016 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, May-June 2016, Las Vegas, NV.
Abstract: 
In this paper, we have studied the microstructure evolution of one-year room-temperature-aged Through-Silicon Via (TSV) copper after annealing the TSV samples at 300 °C, 400 °C and 500 °C for 180 minutes. Hardness and elastic modulus values are obtained by using nano-indentation technique. The hardness and elastic modulus values decrease as annealing temperature increases. The microstructure of copper (Cu) is examined to obtain grain size and texture, using electron backscatter diffraction (EBSD). Copper grain growth, if any, is studied under different annealing temperatures. There was no observable grain growth for the annealing temperatures studied in this work. Moreover, microstructure variation at different locations within a Cu TSV is also studied.
Link to Paper: 
http://ieeexplore.ieee.org/document/7517533/