Design and Development of Stress-Engineered Compliant Interconnect in Microelectronic Packaging

Citation: 
Ma, L., Sitaraman, S. K., Zhu, Q., Klein, K., and Fork, D., “Design and Development of Stress-Engineered Compliant Interconnect in Microelectronic Packaging,” Chapter 21, Nanopackaging: Nanotechnologies and Electronics Packaging, Ed. James E. Morris and Debendra Malik, Springer, 2008.